Primary (Main) Memory
· Memory is that part of the machine where programs and data are stored.
· The basic unit of memory is the binary digit, called a bit which can be a 1 (high) or a 0 (low).
· Memories consist of a number of cells (locations) each of which stores a piece of information. Each cell is assigned a number, called its address, by which the information contained within can be accessed.
· If a memory space has n cells, the addresses will range from 0 to n-1.
· All cells in a memory contain the same number of bits. If a cell consists of k bits, it can hold any one of 2k different bit combinations.
· If an address has m bits, the maximum number of cells directly addressable is 2m.
· The number of bits in an address determines the address space (directly addressable cells in memory) and is completely independent of the number of bits per cell.
· The diagram shown illustrates three ways of organizing a 96-bit memory.
· The significance of the cell is that it is the smallest addressable unit. In recent years, most manufacturers have standardized on an 8-bit cell, which is called a byte. Bytes are grouped into words.
· A machine with a 16-bit word has 2 bytes/word, whereas a machine with 32-bit words has 4 bytes/word.
· A 16-bit machine will have 16-bit registers and instructions, whereas a 32-bit machine will have 32-bit registers and instructions for moving, adding, subtracting, etc.
· A 16-bit computer, for example, will often have memory words interpreted as two bytes, the Low-order or Least Significant Byte (LSB), and the high-order or Most Significant Byte (MSB).
· An 8-bit byte can be further partitioned into 4-bit sections called "nibbles". Thus two nibbles constitute a byte.
· Computer memories can make errors due to voltage spikes on the power line and other causes. Most memory schemes use error-detecting and/or error-correcting codes.
· Extra bits are added to each memory word in a special way such that when the word is read out of memory, the extra bits can be used to detect errors.
· Suppose that a memory word consists of m data bits to which r check bits are added. Then we obtain an n-bit code-word containing m data and r check bits.
· One of the most popular error-correcting codes is the Hamming code. Given any two codewords say, 10001001 and 10110001, a bitwise EXCLUSIVE OR of the codewords is computed to determine how many corresponding bits differ.
· The number of bit positions in which the two codewords differ is called the Hamming distance. It's significance is that if two codewords are a Hamming distance d apart; it will require d single-bit errors to convert one into the other.
· The error-detecting and error-correcting properties of a code depend on its Hamming distance.
· A Hamming code with a distance d guarantees detecting all error patterns of (d - 1) or fewer errors.
· A Hamming code with distance d guarantees correcting all error patterns of t = [(d - 1)/2] or fewer errors.
· The parameter t = [(d - 1)/2] is called the random-error-correcting capability of the code. The code is referred to as a t-error-correcting code.
· For example, a code with a distance of 5 will be able to correct 2 errors or less.
· In a Hamming code, r parity bits are added to an m-bit word, forming a new word of length m+r bits.
· The bits are numbered starting at 1, with bit 1 the leftmost (high-order) bit. All bits whose bit number is a power of 2 are parity bits; the rest are used for data.
· For example, with a 16-bit word, 5 parity bits are added. Bits 1, 2, 4, 8, and 16 are parity bits, and all the rest are data bits.
· Each parity bit checks specific bit positions; the parity bit is set so that the total number of 1's in the checked positions is even.
· In general, bit b is checked by those bits b1, b2, bj such that b1 + b2 + .... + bj = b. For example, bit 5 is checked by bits 1 and 4 because 1 + 4 = 5. Likewise, bit 19 is checked by bits 1, 2 and 16 because 16 + 2 + 1 = 19.
· The bit positions checked by the parity bits are:
Bit 1 checks bits 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21
Bit 2 checks bits 2, 3, 6, 7, 10, 11, 14, 15, 18, 19
Bit 4 checks bits 4, 5, 6, 7, 12, 13, 14, 15, 20, 21
Bit 8 checks bits 8, 9, 10, 11, 12, 13, 14, 15
Bit 16 checks bits 16, 17, 18, 19, 20, 21
· For a 16-bit memory word 1111000010101110, the 21-bit codeword will be 001011100000101101110 using the procedure above.
· Now consider what would happen if bit 5 became corrupted and got inverted. The new codeword would now be 001001100000101101110. The five parity bits will be checked with the following results:
Parity bit 1 incorrect (contains five 1's - odd)
Parity bit 2 correct (contains six 1's - even)
Parity bit 4 incorrect (contains five 1's - odd)
Parity bit 8 correct (contains two 1's - even)
Parity bit 16 correct (contains four 1's - even)
· The corrupted bit is determined as follows:
· Since both Parity bits 1 and 4 compute to an incorrect (odd) parity, the error must be one of the bits common to both lists, namely 5, 7, 13, 15 or 21.
· However, parity bit 2 is correct, eliminating 7 and 15.
· Similarly, parity bit 8 is correct, eliminating 13.
· Finally, parity bit 16 is correct, eliminating 21.
· The only bit left now is bit 5, which is the one in error. Since it was read as a 1, it is inverted to a 0.
· A simple method for finding the incorrect bit is to compute all the parity bits and add up all the incorrect parity bits. The resulting sum will be the position of the incorrect bit.
· In the above example, parity bits 1 and 4 are incorrect. The sum is (4+1) = 5. Bit position 5 is incorrect.
· System performance is degraded considerably when a fast device has to wait for a slower memory system to access data.
· The device may be an I/O device or the CPU, and the memory system may be main memory or an external device.
· One way to mitigate the performance degradation due to slow memory is to incorporate a cache memory into the system.
· Cache memories are small high-speed buffers used for holding recently accessed data and neighboring data in main memory.
· The CPU issues Read/Write requests using addresses that refer to locations in main memory.
· The cache control circuitry determines the requested word currently exists in cache memory.
· If it is (cache hit), the word is delivered to the CPU.
· If not (cache miss), the block containing the word is loaded into cache.
· The observation that the memory references made in any short time interval tend to use only a small fraction of total memory is called the locality principle and forms the basis of all caching systems.
· The general idea is that when a word is referenced, it and some of its neighbors are brought it from the slower main memory to cache, so that the next time it is used it can be accessed much faster.
· There are two reasons why cache works so well. First, the cache operates in parallel with the CPU. That is, the additional words in the block are loaded into the cache after the required word is delivered to the CPU.
· The new words are available to the CPU immediately after it finishes using the current word, at cache speeds.
· Second, by virtue of the principle of locality of reference, the CPU is most likely to request these new words. Hit rates of 90% are not uncommon.
· If a word is read or written k times in a short interval, the computer will need 1 reference to slow memory and k-1 references to cache. The larger k is, the better the overall performance.
· Let c = cache access time, m = main memory access time, and h = hit ratio then, h = (k-1)/k. The miss ratio is 1-h.
· The mean access time = c + (1-h)m.
· As an example, if a computer has a cache access time of 10 nsec, a main memory access time of 60 nsec, and a hit rate of 90%, the average access time will be 16 nsec.
· In the above example, without the cache the machine will have an average access time of 60 nsec.
· Main memory and cache are divided into fixed-size blocks. In cache memory these are called cache lines.
· When a miss occurs, the entire cache line is loaded from main memory into the cache, not just the word required.
· For example, with a 64-byte line size, a reference to main memory address 256 will pull the line consisting of bytes 256 to 319 into cache.
· The bigger the cache, the better it performs, but also the more it costs.
· The size of the cache line is also important, as well as how cache keeps track of words currently held. These issues will be discussed later in the course.
· Another issue is whether instructions and data are kept in the same cache (unified) or separate (split) cache systems.
· Unified cache is a simpler design but will have to balance between data and instruction fetches.
· The trend these days is toward split cache (Harvard architecture).
· The number of caches is also important. Current designs have primary cache on chip, a secondary cache off chip but in the same package as the CPU, and a third cache still further away.
· Modern computers use larger memory units called SIMMs (Serial Inline Memory Modules) or DIMMs (Dual Inline Memory Modules), depending on whether it has a row of connectors on one side or both sides of the board.
· Each SIMM is an assembly of several chips on a separate, smaller board that plugs into a single socket on motherboard.
· SIMMs different sizes can use the same socket. For example, 1M x 8, 4M x 32, and 16M x 8 bit SIMMs all use a 30-pin socket.
· Similarly, 1M x 32, 2M x 32, and 8M x 32 bit SIMMs all use a 72-pin socket.
· The advantage of this is that SIMMs occupy a smaller amount of space on the motherboard and allow for easy expansion is a larger SIMM uses the same socket as a smaller SIMM.
· The current standard is to use DIMMs. A DIMM delivers 64 bits at once.