- Memory is an essential component of every computer that is used for storing both instructions and data. The basic building blocks of memory are gates and
these blocks are combined to produce larger memories.
 

- Latches

• A latch is simply a circuit that "remembers" previous input values or "latches" on to a previous state.
• A simple 1-bit memory can be created using two NOR or NAND gates. These circuits are called SR (Set or Reset) latches. It has two outputs Q   and Q (not)  which are complementary.
• The circuit has an initial state i.e. Q can start of as a 1 or 0. Setting the S input to a 1 results in Q being set to a 1. Conversely, setting R to a 1 results in Q being set  to 0.
• In effect, the circuit remembers whether S or R was last on.

- Clocked SR latches

•  To prevent the latch from changing state except at specified intervals, a clock is provided with additional gates. This circuit is called a clocked SR latch.
• With the clock cycle in a low state both SR inputs will be low and therefore the latch will not change state. When the clock is high, the effect of the AND gates vanishes and the latch becomes sensitive to the S and R inputs.

- Clocked D latches

• A further technique to ensure the integrity of the SR latch is to provide only one input D. This reduces the possibility of both inputs going to a 1 state and thus causing a nondeterministic state.
• With D = 1 and the clock = 1, the latch is driven into a 1 state. With D = 0 and the clock = 0, the latch is driven into a 0 state.
• In effect, when the clock is high, the current value of D is sampled and stored in the latch. This clocked D latch is a true 1-bit memory. The stored values is always available at Q and a new value from D can be stored into memory when the clock is high.

- Flip-Flops
 

• Flip-Flops are actually D clocked D Latches, the difference being that the D latch will have a transition change when the clock is high, the F/F has a transition change when the clock is going from 0 to 1 or 1 to 0.
• In other words, the flip-flop is edge triggered, whereas a latch is level triggered.

- Registers
 

• A register is simply a set of edge triggered D latch's(flip-flop's) with clear and preset signals. The set line forces the circuit into a 1 state and the clear forces a 0 state i.e. reset.
• A typical configuration is a set of flip-flops on a single chip used as an 8-bit register (memory block).

- Memory Organization
 

• Since each F/F requires two pins, D and Q, in addition to control pins, it is quite clear that the larger memory configurations will result in a lack of pins on larger memory chips.
• Therefore, a different organization is required in which the number of pins grows logarithmically rather than linearly with memory capacity.
• Refer to Fig 3-29. This is a 4 X 3 memory or a memory with four 3-bit words. Each operation reads or writes a full 3-bit word.
• The memory circuit has 8 I/P lines and 3 O/P lines. Three of the inputs are data lines : I0, I1 and I2.
• Two of the inputs are used for addressing : A0 and A1. The remaining three inputs are used for control : CS (Chip Select), RD (Read/Write) and OE (Output Enable).
• The three outputs are used for data : D0, D1 and D2. A memory such as this can be packaged into a 14-pin chip, including power and ground.
• To select this memory chip the CS is set high and set RD high (RD = 1 for read and 0 for write). The address lines are set to indicate which of the four 3-bit words is to be read or written.
• For read operations, the data inputs are not used, but the word selected is placed on the data output lines. For a write operation, the bits present on the data input lines are loaded into the selected memory word; the data output lines are not used.

- Memory Chips
 

• The 4 x 3 memory can easily be extended to larger sizes by simply adding F/F's and I/O lines.
• For example, to extend it to 4 x 8 we add five more columns of four F/F's each, as well as five more input and output lines.

• To go from 4 x 3 to 8 x 3 we must add four more rows of three F/F's each, as well as an address line A2. This type of a structure requires the number of words in the memory to be a power of 2 for maximum efficiency, but the number of bits in a word is arbitrary.
• There are various ways of organizing a given memory size on a chip. For example, two possible organizations for a 4-Mbit chip are 512K x 8 and 4096K x 1.
• A 512K x 8 chip, 19 lines are needed to address the selected byte and 8 data lines are needed for loading and storing data.
• The 4096K x 1 chip requires a different addressing scheme to access the selected bit. The chip is organized as a 2048x2048 matrix of 1-bit cells.
• It uses 11 pins for addressing but only one line is needed for loading and storing data.
• To address the chip, a row is fist selected by placing its 11-bit number on the address pins. RAS (Row Address Strobe) is then asserted.
• Next, the column number is placed on the address pins and the CAS Column Address Strobe) is asserted. At this point the required bit is completely addressed and is outputted.

- RAMs and ROMs
 

• The memories discussed so far can all be read form and written to. This class of memory is called RAM (Random Access Memory).
• Static RAM's use circuits similar to the D-latch and will retain their contents as long as power is kept on.
• Dynamic RAM's do not use D latches, instead they use arrays of tiny capacitors, each of which can be charged or discharged to store a 1 or 0. Since electric charge tends to decay with time, each bit in a dynamic RAM must be refreshed every few milliseconds to prevent a loss of data.
• Technology has advanced to a state where today we have many, many different types of RAM chips, both static and dynamic.
• For many years in the computer industry there was only one type of dynamic RAM used, the Page Mode RAM and later the Fast Page Mode RAM.
• Currently, significant advances in CPU architecture and performance have necessitated the design of faster RAM types.
• The first thing to get around the slowness of the main memory was the introduction of caches in the CPUs and on the motherboards.
• However even cache is not enough to keep a fast CPU from slowing down due to slower RAM.
• The new technology includes EDO (Extended Data Out), BEDO (Burst EDO) and SDRAM (Synchronous DRAM) memory.

- Fast Page Mode RAM (FPM RAM)
 

• The oldest and least sophisticated among all these RAM types. It nowadays comes in two different flavors, 70ns and 60ns access time.
• The 60 ns is used in a Pentium architecture with a bus speed of 66 MHz (100,133,166 and 200 MHz Pentium CPUs).
• This kind of RAM is also used on video cards, called VRAM and sometimes with an access time of only 48 nsec in that application.
• VRAM or Video RAM is also referred to as dual ported, which means it can be accessed by the Graphics Adapter independently of the CPU accesses via the second port.
• Therefore, the adapter doesn't have to wait for the CPU access to finish and vice versa - this makes it quite a bit faster than DRAM.
• FPM is a standard DRAM where any number of accesses to the currently open row can be made while the RAS (Row Access Signal) signal is kept active.
• The Fast Page Mode means, that the RAM logic 'assumes', that the next access will be in the same row, saving time if this assumption turns out to be true.

- Extended Data Output RAM (EDO RAM)
 

• This technology entails a minor change to the FPM architecture to improve the DRAM's page mode cycle time.This type of DRAM is designed to access nearby memory locations (sequential accesses) faster than FPM DRAM.
• EDO-DRAM allows the data outputs to be kept active after the CAS (Column Access Signal) signal goes inactive, using an additional signal OE (Output Enable) to control the data outputs. A set of gates latches the output value till read by the CPU, which is important for fast CPUs.
• This can be used in pipelined systems for overlapping accesses where the next cycle is started before the data from the last cycle is removed from the bus.
• Stated another way, the memory can continue to output data from one address while setting up a new address, for use in pipelined CPUs as the Pentium series.
• EDO DRAM is primarily used with Intel's Pentium processors since with slower processors there is no significant performance gain.
• To make use of the advanced features of EDO an appropriate chipset, such as Triton, must be used.
• A chip set is a collection of integrated circuits (chips) that are designed to be used together for some specific purpose. E.g. control circuitry in an PC architectures.
• Triton is Intel's Pentium core logic chip set. In addition to the traditional features, this chip set supports: EDO DRAM to increase the bandwidth of the DRAM interface; "pipelined burst SRAM" for a cheaper, faster second level cache; "bus master IDE" control logic to reduce processor load; a plug and play port for easy implementation of functions such as audio.
• The Triton I chipset (official name 82430FX) consists of 4 chips: one 82437FX TSC (Triton System Controller), two 82438FX TDP (Triton Data Path), and one 82371FB PIIX (PCI IDE Xcellerator).
• It supports PB Cache, EDO DRAM, and a maximum PCI and memory burst data transfer rate of 100 megabytes per second.
• In early 1995, EDO DRAM was available for computers from Micron, Gateway 2000, and Intel; since then other manufactures followed suit.
• Note that in comparison to Burst EDO, EDO is sometimes referred to as "Standard EDO".
• It comes in three flavors 70ns, 60ns and 50ns. The 60ns version requires a bus speed of 66 MHz. With the new Triton HX or VX chipset you also can take advantage of 50ns EDO.

- Burst EDO (BEDO) RAM

• A modification to EDO which includes a pipeline stage and a two-bit burst counter.
• After the applying the CAS-address, all read and write cycles occur in a four cycle bursts. The bursts wrap around on a four-byte boundary which means that only the two least significant bits of the CAS address are modified internally to produce each address of the burst sequence.
• Once the first page address has been applied, the DRAM itself provides the address of the next memory location to be accessed.
• This address prediction eliminates the delay associated with detecting and latching an externally provided address to the DRAM controller.
• Consequently, burst EDO bus speeds will range from 40MHz to 66MHz, well above the 33MHz bus speeds that can be accomplished using Fast Page Mode or EDO DRAM.

- Synchronous DRAM (SDRAM)
 

• A DRAM technology that uses a clock to synchronize signal input and output on a memory chip. The clock is coordinated with the CPU clock so the timing of the memory chips and the timing of the CPU are "in synch."
• A key feature of SDRAM is its ability to increase the overall system performance of the computer by reducing the time in executing commands and transmitting data.
• The SDRAM architecture provides for two row addresses of the DRAM to be opened simultaneously.
• Specifically, it makes the implementation of control interfaces easier, and it makes column access time much quicker.
• This technique allows I/O transactions to take place every clock cycle. Once the burst has started, all remaining bits of the burst length are delivered at a 10 ns rate. In doing so, a seamless data rate of 100MHz can be achieved to read or write the entire device.
• SDRAM includes an on-chip burst counter that can be used to increment column addresses for very fast burst accesses. To work with up to 100 MHz clock speeds, SDRAMs are designed with two internal banks.
• This allows one bank to get ready for access while the other bank is being accessed. This means that SDRAM allows new memory accesses to be initiated before the preceding access has been completed.
• Having the ability to burst I/O without new addresses means that the design can be optimized for cache fills at the system bus frequency.
• The burst length and latency can be programmed during a special entry cycle and therefore allows us to optimize the same device for many different system applications.

- Read Only Memory (ROM)
 

• ROM's are used when the data must remain stored and neither the data or program will be changed. The data is written in during it's manufacture and thereafter cannot be erased or changed.
• PROM's (Programmable Read ONly Memory) is similar to ROM except that it can be programmed (once) in the field, thus giving more flexibility and reducing turnaround time.
• EPROM's (Erasable PROM) can be field-programmed as well as be field- erased. These are far more economical than PROM's because they can be reused.
• EEPROM's (Electrically Erasable PROM) also called EAROM (Electrically Alterable ROM) is by far the best in terms of flexibility and ease of use.
• These can be erased by applying electrical pulses to it.
• Flash memory is a more recent type of EEPROM. It is block erasable and rewritable. This is used in digital cameras as "film" for storing images.
• Flash memory circuits tend to wear out over time (10,000 erasures).