• Each CPU has a set of pins through which it communicates with the outside world. The pin functions define the interaction of the processor with memory and I/O devices.

• The pins are divided into three categories: address, data and control. The pins are connected to their counterparts on the memory and I/O chips via a set of parallel wires called a bus.

• To fetch an instruction, the CPU first puts the memory address of that instruction on it's address pins. Then it asserts a control line to inform the memory that it wants to read a word.

• The memory replies by placing the requested word on the CPU data pins. It then asserts a signal indicating that the operation is done. When the CPU sees this signal, it accepts the word and carries out the instruction.

• Two of the key parameters that determine the performance of a CPU are the number of address pins and the number of data pins (i.e. the bus size).

• A chip with m address pins can address up to 2^m bytes of memory. Common values of m are 16, 20, 24, 32 and 64.

• Similarly, a chip with n data pins can read or write an n-bit word in a single operation. Common values of n are 8, 16 and 32. A processor with 8 data pins will take four operations to read a 32-bit word, whereas one with 32 data pins can do the same job in one operation.

• In addition to address and data pins, each CPU has some control pins. The control pins regulate the flow and timing of data to and from the CPU as well as some other miscellaneous functions.

• The control pins can be roughly grouped into the following major categories:

• These are mostly outputs from the CPU to the bus (i.e. inputs to memory and I/O) indicating whether the CPU wants to read or write or perform some other function.

• These are inputs from I/O devices to the CPU.
• The processor tells an I/O device to start the operation, and then performs some other tasks while the slow I/O device is doing it's work. The I/O asserts a signal on one of the interrupt pins when it's task is completed. The CPU will then service the I/O device.

• These pins are required to regulate the traffic on the bus, in order to prevent two devices from accessing the bus simultaneously.

(4). Coprocessor Signaling

• These pins are used to facilitate communication between the CPU and it's coprocessor.

• These days these are mostly graphics coprocessors.
• Special pins are provided for making and granting various requests.

(5). Status and Miscellaneous

• These provide or accept status information as well as facilitate functions such as resetting the computer, and still others are used to assure compatibility with older I/O chips.

Computer Buses
 

• A bus is defined as a common electrical pathway between multiple devices. One example of this is the system bus on all microcomputers which consists of 50 to 100 parallel copper wires etched on to the motherboard with connectors spaced at regular intervals for plugging in memory and I/O boards.

• The collection of paths connecting the various modules is called the interconnection structure. The design of this structure will depend on the exchanges that must be made between modules.

• The diagram shown suggests the types of exchanges that are required based on the major forms of input and output for each module type:

• Memory bus: Allows a data word to be read from or written into memory. The nature of the operation is specified by the Read and Write control signals. The location of the operation is specified by an address.

• I/O bus: Allows data to be exchanged between the CPU and other I/O devices. There two operations, read and write. Each external device is connected to a port which has a unique address.

• Internal CPU bus: Allows data to be exchanged between the functional units within the CPU.

• In order to make it possible for boards designed by third parties to attach to the system bus, there must be well-defined rules about how the bus works, and which all devices attached to it must obey. These set of rules are called the bus protocol.

• There a number of bus standards currently in use:

EISA, VESA bus - 80386 80486 machines

PCI bus - Latest CPU bus systems

SCSI - Latest CPU bus systems

USB - Latest CPU bus systems

Firewire bus - Consumer Electronics

VME bus - Physics lab equipment (680x0 CPUs)

• Devices attached to a bus can be categorized as active, those that can initiate bus transfers, or passive, those that wait for requests. The active ones are called masters and the passive ones slaves.

• When the CPU commands a disk controller to read or write a block, the CPU is acting as a master and the disk controller is acting as the slave. Later on the disk controller may act as a master when it commands the memory to accept the words it is reading from the drive.

• There are several combinations of this master/slave relationship. Under no circumstances can the memory ever assume master status.

• Bus masters are connected to the bus by a chip called a bus driver. Similarly slaves are connected to the bus by a bus receiver. For devices that can act as both the slave and master, a combination chip called a transceiver is used.

• Like a CPU, a bus also has address, data and control lines.

• The principal bus design issues are bus clocking, arbitration mechanism, and bus operations. These parameters have a substantial impact on the speed and bandwidth of the bus, hence they will determine the performance of the bus.

Bus Clocking

• Buses can be divided into two main categories depending on how they are clocked.

• A synchronous bus relies on a master clock and performs tasks that take up bus cycles.

• An asynchronous bus does not rely on a common clock but relies on control signallign between various devices connected to it.

Synchronous Buses

• A synchronous bus has a line driven by a crystal oscillator (clock). The frequency of this clock is generally between 5 MHz and 100 MHz. All bus activities take an integral number of cycles, called bus cycles.
• Consider the timing diagram shown on Fig 3-37(a). The clock frequency is 40 MHz, which gives a bus cycle of 25 nsec. Assume that a read operation takes a total 40 nsec from the time the address is stable.

• The first cycle starts at T₁ and the third one ends at the rising edge of T₄.

• Part way through T1 the CPU puts the address of the word it wants on the address lines. The data is obtained halfway into T₃.
• MREQ (Memory Request) is asserted to indicate that memory is being accessed (as opposed to an I/O device). RD (Read Data) is asserted to indicate a read operation.

• Nothing happens during T₂, to give the memory time to decode the address and put the data on the bus.

• At the falling edge of T₃ the CPU will read the data lines and will store the data in an internal register. Having read the data, the CPU negates MREQ and RD.

• If memory is unable to respond fast enough (i.e. within a specified time), it will assert a WAIT signal prior to the falling edge of T₂. This action will insert wait states (extra bus cycles) until the memory is finished and negates WAIT.

• The timing specification provided shows the additional timing parameters for the bus. For example, T_AD is the time interval between the rising edge of the T₁ clock and the address lines being set. This is specified as less than or equal to 11 nsec.

• This means that the CPU manufacturer will have to ensure that the CPU will output the address to be read within 11 nsec of the midpoint of the rising edge of T₁.

• Similarly, the specification requires that the data be available at least 5 nsec before the falling edge of T₃ (T_DS).

• The combination of T_AD and T_DS means that in the worst case, the memory will have only 46.5 nsec from the time the address appears until it must produce the data.

• Similarly, the constraints on T_M and T_RL mean the MREQ and RD will both be asserted within 8 nsec from the T₁ falling clock.

• In the worst case, the memory chip will have only 37 nsec after the assertion of MREQ and RD to get its data onto the bus.
• There are several disadvantages to using synchronous buses:

• Since everything works in integral multiples of the bus clock, if a particular operation requires 3.1 cycles, it will have to be stretched to 4.0 because fractional cycles are forbidden.

• Once a bus cycle has been selected, and memory and I/O cards have been built for it, it is difficult to take advantage of future improvements in technology.

• Conversely, if a bus has a heterogeneous collection of devices of varying speeds, the bus has to be geared to the slowest one thus reducing the potential speed of the fast ones.

Asynchronous Buses

• The problem of mixed technology can be handled by an asynchronous bus. This type of a bus has no master clock. Instead of tying everything to the clock, when the bus master has asserted the address, MREQ, RD, and anything else it needs to, it then asserts a special signal called MSYN (Master SYnchronization).

• When the slave sees MSYN, it performs the task as fast as it can. When it is done, it asserts SSYN (Slave SYNchronization).

• As soon as the master sees SSYN asserted, it knows that the data is available, so it latches them, and negates the address lines, along with MREQ, RD, and MSYN.

• When the slave sees the negation of MSYN, it knows that the cycle has been completed, so it negates SSYN and we are back to the original situation.

• The sequence of a set of signals which facilitate an operation such as the one described is known as a full handshake. The essential part consists of four events:

1. MSYN is asserted.

2. SSYN is asserted in response to MSYN.

3. MSYN is negated in response to SSYN.

4. SSYN is negated in response to the negation of MSYN.
 

• Clearly, full handshakes are timing independent. Each event is caused by a prior event, not by a clock pulse. If a particular master-slave pair is slow, that in no way affects a subsequent master-slave pair that is much faster.

• The asynchronous bus is clearly a more efficient one, but the fact is that most buses are synchronous. This is because it is easier (cheaper) to build a synchronous system.

Bus Arbitration

• There is a definite requirement for various devices to assume a bus master status (as opposed to the CPU only). For example, I/O chips need to become bus master to read and write memory and to cause interrupts.

• This implies that there has to be some bus arbitration mechanism to prevent several devices from becoming bus masters at the same time. Arbitration mechanisms can be centralized or decentralized.

• In centralized arbitration, a single bus arbiter determines who goes next. The bus contains a single wired-OR request line that can be asserted by one or more devices at any time.

• There is no way for the arbiter to determine how many devices have requested the bus. The only categories it can distinguish are: some requests and no requests.

• When the bus arbiter sees a bus request, it issues a grant by asserting the bus grant line. This line is wired through all the I/O devices in series. When the device closest to the arbiter sees the grant, it checks to see if it made a request. If so, it takes over the bus but does not propagate the grant any further along the line.

• If the device had not made a request, it propagates the grant further down the line. In this way the grant moves down the line until some device accepts the grant and takes the bus.

• This scheme is called daisy chaining and it has the property that devices are effectively assigned priorities depending on close to the arbiter they are. The closest device wins.

• To get around the implicit priorities based on distance from the arbiter. Many buses have multiple priority levels. For each priority level there is a bus request line and a bus grant line.

• Each device attaches to one of the bus request levels, with more time critical devices attaching to the higher priority ones.

• If multiple priority levels are requested at the same time, the arbiter issues a grant only on the highest priority one. Among devices of the same priority, daisy chaining is used.

• With decentralized bus arbitration there is no bus arbiter. For example, a computer can have 16 prioritized bus request lines, one per device.

• When a device wants to use the bus, it asserts its request line. All devices monitor the request lines, so at the end of each bus cycle, each device knows whether it was the highest priority requester, and thus whether it is permitted to use the bus during the next cycle.

• Another type of decentralized bus arbitration scheme uses only three lines, no matter how many devices are present. The first line is a wired-OR line for requesting the bus. The second line is called BUSY, and is asserted by the current bus master. The third line is used to arbitrate the bus and is daisy chained through all the devices.

• When no device wants the bus, the asserted arbitration line is propagated through to all devices. To acquire the bus, a device first checks to see if the bus is idle and the arbitration signal is receiving, IN, is asserted.

• If IN is negated, it may not become bus master. If IN is asserted, the device negates OUT, which requires every device downstream to negate IN and OUT. Ultimately, only one device will have IN asserted and OUT negated. That device will become bus master, asserts BUSY and OUT, and begins the transfer.

Bus Operations

• In addition to read (and write) cycles, some synchronous buses support block transfers. When a block read is started, the bus master tells the slave how many bytes are to be transferred, by putting the byte count on the data lines during T₁.

• Instead of returning one byte, the slave outputs one byte during each cycle until the count has been exhausted. An extra signal (BLOCK) is asserted to indicate a block transfer is required.

• In this example, a block read of n bytes would take n + 2 cycles instead of 3n.

• Interrupt Handling

• Another important bus use is handling interrupts. When a CPU commands an I/O device to perform a task, it usually expects an indication when the task is complete. This indication is called an interrupt signal. The interrupt signaling requires the bus.

• Since multiple devices may generate an interrupt simultaneously, the same kind of arbitration problems are present here that we had with ordinary bus cycles.

• The usual solution is to assign priorities to devices, and use centralized arbiter to give priority to the most time critical devices. Standard interrupt controller chips exist and are widely used. Current architectures all use the Intel 8259A chip, commonly referred to as the PIC (Peripheral Interrupt Controller).

• Upto eight I/O controller chips can be directly connected to the eight IR(x) (Interrupt Request) inputs. For control of more modules, a cascade arrangement can be used to handle up to 64 modules. Any device wanting to cause an interrupt asserts its input line.

• When one or more inputs are asserted, the 8259A asserts INT (INTerrupt), which directly drives the input pin on the CPU. When the CPU is able to handle the interrupt, it sends a pulse back to the PIC on INTA (INTerrupt Acknowledge).

• At that point the PIC is expected to specify which input caused the interrupt by outputting that input's number on the data bus.

• The CPU hardware then uses that number to index into a table of pointers, called interrupt vectors, to find the address of the procedure to run to service the interrupt (interrupt service routines).